// RAM module of Deep Learning on FPGA
// by Toshio Iwata at digitalfilter.com 2019/08/24
//
module Ram (CLK, WR_N, WRADDR, WRDATA, RDADDR, RDDATA);

input CLK;
input WR_N;

input [7:0] WRADDR;
input [15:0] WRDATA;
input [7:0] RDADDR;
output [15:0] RDDATA;

reg [15:0] ramdata [255:0];
reg [15:0] rddata_int;

//-------------------------------------------------
always @(posedge CLK)
begin

  if (WR_N == 0)
    ramdata[WRADDR] <= WRDATA;

end

//-------------------------------------------------
always @(posedge CLK)
begin
  rddata_int = ramdata[RDADDR];
end

assign RDDATA = rddata_int;

endmodule