signal a0_D, a1_D, a2_D, b1_D, b2_D : std_logic_vector(15 downto 0);
	signal RDATAOUT_C : std_logic_vector(15 downto 0);

-- Parts Name: Low Shelving Filter
-- Parts Number: U_6
-- Sampling Frequency =    44010.0
-- Cutoff =      500.0
-- Gain =       10.0
-- Slope =   1.0000
-- Quantized by 15 [bits]
    a0_D <= "0011111111111111" when sw0 = '0' else "0100000111101001";
    a1_D <= "0000000000000000" when sw0 = '0' else "1000010100001001";
    a2_D <= "0000000000000000" when sw0 = '0' else "0011100110011100";
    b1_D <= "0000000000000000" when sw0 = '0' else "0111101100101000";
    b2_D <= "0000000000000000" when sw0 = '0' else "1100010010101011";

MuxIir_C : MuxIir port map (
          RST_N => RST_N,
          MCLK => CLK,
          FSCLK => LRCLK_dly,
          A0 => a0_C,
          A1 => a1_C,
          A2 => a2_C,
          B1 => b1_C,
          B2 => b2_C,
          XIN => RDATAOUT_B,
          YOUT => RDATAOUT_C);

MuxIir_D : MuxIir port map (
          RST_N => RST_N,
          MCLK => CLK,
          FSCLK => LRCLK_dly,
          A0 => a0_D,
          A1 => a1_D,
          A2 => a2_D,
          B1 => b1_D,
          B2 => b2_D,
          XIN => RDATAOUT_C,
          YOUT => RDATAOUT);