signal a0_A, a1_A, a2_A, b1_A, b2_A : std_logic_vector( 15 downto 0 );
  signal a0_B, a1_B, a2_B, b1_B, b2_B : std_logic_vector( 15 downto 0 );
  signal a0_C, a1_C, a2_C, b1_C, b2_C : std_logic_vector( 15 downto 0 );

  signal RDATAOUT_A, RDATAOUT_B : std_logic_vector( 15 downto 0 );

-- Butterworth LPF
-- Sampling Frequency =   44100.0
-- cutoff1 =    3000.0
-- Order = 6th
-- Quantized by 15 [bits]
-- **** 1st biquad ****
     a0_A <= "0011111111111111" when sw0 = '0' else "0000001010011010";
     a1_A <= "0000000000000000" when sw0 = '0' else "0000010100110100";
     a2_A <= "0000000000000000" when sw0 = '0' else "0000001010011010";
     b1_A <= "0000000000000000" when sw0 = '0' else "0110100100101111";
     b2_A <= "0000000000000000" when sw0 = '0' else "1100110001101001";
-- **** 2nd biquad ****
     a0_B <= "0011111111111111" when sw0 = '0' else "0000001000111010";
     a1_B <= "0000000000000000" when sw0 = '0' else "0000010001110100";
     a2_B <= "0000000000000000" when sw0 = '0' else "0000001000111010";
     b1_B <= "0000000000000000" when sw0 = '0' else "0101101000010000";
     b2_B <= "0000000000000000" when sw0 = '0' else "1101110100000110";
-- **** 3rd biquad ****
     a0_C <= "0011111111111111" when sw0 = '0' else "0000001000001110";
     a1_C <= "0000000000000000" when sw0 = '0' else "0000010000011101";
     a2_C <= "0000000000000000" when sw0 = '0' else "0000001000001110";
     b1_C <= "0000000000000000" when sw0 = '0' else "0101001100101010";
     b2_C <= "0000000000000000" when sw0 = '0' else "1110010010011100";

MuxIir_A : MuxIir port map (
          RST_N => RST_N,
          MCLK => CLK,
          FSCLK => LRCLK_dly,
          A0 => a0_A,
          A1 => a1_A,
          A2 => a2_A,
          B1 => b1_A,
          B2 => b2_A,
          XIN => RDATAIN,
          YOUT => RDATAOUT_A);

MuxIir_B : MuxIir port map (
          RST_N => RST_N,
          MCLK => CLK,
          FSCLK => LRCLK_dly,
          A0 => a0_B,
          A1 => a1_B,
          A2 => a2_B,
          B1 => b1_B,
          B2 => b2_B,
          XIN => RDATAOUT_A,
          YOUT => RDATAOUT_B);

MuxIir_C : MuxIir port map (
          RST_N => RST_N,
          MCLK => CLK,
          FSCLK => LRCLK_dly,
          A0 => a0_C,
          A1 => a1_C,
          A2 => a2_C,
          B1 => b1_C,
          B2 => b2_C,
          XIN => RDATAOUT_B,
          YOUT => RDATAOUT);