SP_FIR_PS Project Status | |||
Project File: | sp_fir_ps.ise | Current State: | Programming File Generated |
Module Name: | sp_fir_ps |
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No Errors |
Target Device: | xc3s250e-5vq100 |
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10 Warnings |
Product Version: | ISE 9.1i |
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? 10 13 16:23:54 2007 |
SP_FIR_PS Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 139 | 4,896 | 2% | |
Number of 4 input LUTs | 528 | 4,896 | 10% | |
Logic Distribution | ||||
Number of occupied Slices | 814 | 2,448 | 33% | |
Number of Slices containing only related logic | 814 | 814 | 100% | |
Number of Slices containing unrelated logic | 0 | 814 | 0% | |
Total Number of 4 input LUTs | 1,554 | 4,896 | 31% | |
Number used as logic | 528 | |||
Number used as a route-thru | 1 | |||
Number used for Dual Port RAMs | 1,024 | |||
Number used as Shift registers | 1 | |||
Number of bonded IOBs | 9 | 66 | 13% | |
IOB Flip Flops | 6 | |||
Number of Block RAMs | 5 | 12 | 41% | |
Number of GCLKs | 2 | 24 | 8% | |
Number of MULT18X18SIOs | 2 | 12 | 16% | |
Total equivalent gate count for design | 398,841 | |||
Additional JTAG gate count for IOBs | 432 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | ? 10 11 15:38:20 2007 | 0 | 8 Warnings | 10 Infos |
Translation Report | Current | ? 10 11 15:38:31 2007 | 0 | 0 | 0 |
Map Report | Current | ? 10 11 15:38:49 2007 | 0 | 2 Warnings | 3 Infos |
Place and Route Report | Current | ? 10 11 15:40:13 2007 | 0 | 0 | 0 |
Static Timing Report | Current | ? 10 11 15:40:27 2007 | 0 | 0 | 2 Infos |
Bitgen Report | Current | ? 10 11 15:40:49 2007 | 0 | 0 | 0 |