component nios2e is
		port (
			clk_clk                        : in    std_logic := 'X'; -- clk
			reset_reset_n                  : in    std_logic := 'X'; -- reset_n
			sda_external_connection_export : inout std_logic := 'X'; -- export
			scl_external_connection_export : inout std_logic := 'X'  -- export
		);
	end component nios2e;