component nios2e is
        port (
            clk_clk                           : in    std_logic             := 'X'; -- clk
            reset_reset_n                     : in    std_logic             := 'X'; -- reset_n
            thresh_external_connection_export : out std_logic_vector(13 downto 0);         -- export
            scl_external_connection_export    : inout std_logic             := 'X'; -- export
            sda_external_connection_export    : inout std_logic             := 'X' -- export
        );
    end component nios2e;