library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity VideoProc is
   Port ( 
	LED0	: OUT std_logic; 
	LED1	: OUT std_logic; 
	LED2	: OUT std_logic; 
	LED3	: OUT std_logic; 
	LED4	: OUT std_logic; 
	LED5	: OUT std_logic; 
	LED6	: OUT std_logic; 
	LED7	: OUT std_logic; 
	LED8	: OUT std_logic; 
	LED9	: OUT std_logic; 
   CLK : In std_logic;
	RST_N	: IN std_logic );  
end VideoProc ;

architecture RTL of VideoProc is

-------------------------------------------------------------------------------
-- Signal
-------------------------------------------------------------------------------
signal counter32b : std_logic_vector(31 downto 0);

begin

-------------------------------------------------------------- 
gen_counter32b : process( RST_N, CLK )  
begin 
	if( RST_N = '0' ) then
		counter32b <= (others => '0');
	elsif( CLK'event and CLK = '1' ) then
		counter32b <= counter32b + 1;
	end if;  
end process;

  LED0 <= counter32b(23);
  LED1 <= '0';
  LED2 <= '0';
  LED3 <= '0';
  LED4 <= '0';
  LED5 <= '0';
  LED6 <= '0';
  LED7 <= '0';
  LED8 <= '0';
  LED9 <= '0';
  
end RTL;