-------------------------------------------------------------- 
    u0 : component nios2e
        port map (
            clk_clk                          => MCLK,                          --                       clk.clk
            reset_reset_n                    => RST_N,                    --                     reset.reset_n
            pio_1_external_connection_export => dip_sig, -- pio_1_external_connection.export
            pio_0_external_connection_export => led_sig  -- pio_0_external_connection.export
        );

  LED2 <= led_sig(0);
  LED3 <= led_sig(1);
  
  dip_sig(0) <= DIP0;
  dip_sig(1) <= DIP1;