library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cyctop is
   Port ( 
	DIP0	: IN std_logic;
	DIP1	: IN std_logic;
	LED0	: OUT std_logic;
	LED1	: OUT std_logic; 
	LED2	: OUT std_logic; 
	LED3	: OUT std_logic; 
    MCLK : In std_logic;
	RST_N	: IN std_logic );  
end cyctop ;

architecture RTL of cyctop is

-------------------------------------------------------------------------------
-- Signal
-------------------------------------------------------------------------------
signal counter32b : std_logic_vector(31 downto 0);
signal led_sig : std_logic_vector(1 downto 0);
signal dip_sig : std_logic_vector(1 downto 0);

begin

-------------------------------------------------------------- 
gen_counter32b : process( RST_N, MCLK )  
begin 
	if( RST_N = '0' ) then
		counter32b <= (others => '0');
	elsif( MCLK'event and MCLK = '1' ) then
		counter32b <= counter32b + 1;
	end if;  
end process;

  LED0 <= counter32b(25);
  LED1 <= counter32b(26);
  
end RTL;