component AdrsGen port( CLK : in std_logic; RST_N : in std_logic; FFT_START : in std_logic; FFT_SEL : out std_logic; FFT_END : out std_logic; PHASE_K : out std_logic; PHASE_I : out std_logic; FFT_ADDR : out std_logic_vector(9 downto 0); TRI_ADDR : out std_logic_vector(9 downto 0) ); end component; component S_P Port ( RST_N : In std_logic; MCLK : In std_logic; SDATA : In std_logic; LRCLK : In std_logic; BCLK : In std_logic; LDATA : Out std_logic_vector(15 downto 0); RDATA : Out std_logic_vector(15 downto 0) ); end component; component initial_latch Port ( RST_N : In std_logic; MCLK : In std_logic; ADATA : In std_logic; ADATAO : Out std_logic; ABCLK : In std_logic; ABCLKO : Out std_logic; ALRCLK : In std_logic; ALRCLKO : Out std_logic; ALRCLKO2 : Out std_logic ); end component; component TimingGen Port ( CLK : in std_logic; RST_N : in std_logic; CAP_START : in std_logic; CAP_SEL : out std_logic; ALRCLK : Out std_logic; ABCLK : Out std_logic; AMCLK : Out std_logic; ADDRADC : Out std_logic_vector(9 downto 0) ); end component; component TriRom Port ( CLK : In std_logic; CS_N : In std_logic; ADDR : In std_logic_vector(9 downto 0); DATA : Out std_logic_vector(19 downto 0) ); end component; component Ram Port ( CLK : In std_logic; CS_N : In std_logic; WR_N : In std_logic; WRADDR : In std_logic_vector(9 downto 0); RDADDR : In std_logic_vector(9 downto 0); WRDATA : In std_logic_vector(15 downto 0); RDDATA : Out std_logic_vector(15 downto 0) ); end component; component RamCtrl Port ( MCLK : in std_logic ; RST_X : in std_logic ; FFT_ADDR : in std_logic_vector( 9 downto 0 ) ; CAP_SEL : in std_logic ; FFT_SEL : in std_logic ; FFT_SEL_EXT : out std_logic ; REAL_RD_ADDR : out std_logic_vector( 9 downto 0 ) ; IMAG_RD_ADDR : out std_logic_vector( 9 downto 0 ) ; REAL_WR_ADDR : out std_logic_vector( 9 downto 0 ) ; IMAG_WR_ADDR : out std_logic_vector( 9 downto 0 ) ; PHASE_I : in std_logic; CS_0_X : out std_logic ; CS_1_X : out std_logic ; WR_0_X : out std_logic ; WR_1_X : out std_logic ; REAL_RD_DATA : in std_logic_vector( 15 downto 0 ) ; IMAG_RD_DATA : in std_logic_vector( 15 downto 0 ) ; REAL_WR_DATA : out std_logic_vector( 15 downto 0 ) ; IMAG_WR_DATA : out std_logic_vector( 15 downto 0 ) ; FFT_REAL_RD_DATA : out std_logic_vector( 15 downto 0 ) ; FFT_IMAG_RD_DATA : out std_logic_vector( 15 downto 0 ) ; FFT_REAL_WR_DATA : in std_logic_vector( 15 downto 0 ) ; FFT_IMAG_WR_DATA : in std_logic_vector( 15 downto 0 ) ; ADC_ADDR : in std_logic_vector( 9 downto 0 ) ; ADC_DATA : in std_logic_vector( 15 downto 0 ) ; UP_ADDR : In std_logic_vector(9 downto 0); UP_RD_DATA : Out std_logic_vector(15 downto 0); UP_WR_DATA : In std_logic_vector(15 downto 0); UP_OE_N : In std_logic; UP_WE_N : In std_logic; UP_IMAG_SEL : In std_logic ); end component; component butterfly port( MCLK : in std_logic ; RST_X : in std_logic ; PHASE_K : in std_logic ; TRI_RD_DATA : in std_logic_vector( 19 downto 0 ) ; FFT_REAL_RD_DATA : in std_logic_vector( 15 downto 0 ) ; FFT_IMAG_RD_DATA : in std_logic_vector( 15 downto 0 ) ; FFT_REAL_WR_DATA : out std_logic_vector( 15 downto 0 ) ; FFT_IMAG_WR_DATA : out std_logic_vector( 15 downto 0 ) ); end component; ------------------------------------------------------------------------------- -- Signal ------------------------------------------------------------------------------- signal dummy_low : std_logic; signal dummy_high : std_logic; signal AMCLK_sig : std_logic; signal ALRCLK_sig : std_logic; signal ABCLK_sig : std_logic; signal ADATA_latch : std_logic; signal ALRCLK_latch_l : std_logic; signal ALRCLK_latch_r : std_logic; signal ABCLK_latch : std_logic; signal ADC_ADDR_sig : std_logic_vector(9 downto 0) ; signal ADC_DATA_sig : std_logic_vector(15 downto 0) ; signal WR_0_X_sig : std_logic ; -- Real RAM Write Enable signal WR_1_X_sig : std_logic ; -- Real RAM Write Enable signal REAL_RD_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Real RAM Read Data signal IMAG_RD_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Imag RAM Read Data signal REAL_WR_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Real RAM Write Data signal IMAG_WR_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Imag RAM Write Data signal REAL_RD_ADDR_sig : std_logic_vector( 9 downto 0 ) ; -- Real RAM Read Address signal IMAG_RD_ADDR_sig : std_logic_vector( 9 downto 0 ) ; -- Imag RAM Read Address signal REAL_WR_ADDR_sig : std_logic_vector( 9 downto 0 ) ; -- Real RAM Write Address signal IMAG_WR_ADDR_sig : std_logic_vector( 9 downto 0 ) ; -- Imag RAM Write Address signal FFT_REAL_RD_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Real RAM Read Data to FFT signal FFT_IMAG_RD_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Imag RAM Read Data to FFT signal FFT_REAL_WR_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Real RAM Write Data from FFT signal FFT_IMAG_WR_DATA_sig : std_logic_vector( 15 downto 0 ) ; -- Imag RAM Write Data from FFT signal FFT_ADDR_sig : std_logic_vector( 9 downto 0 ) ; -- FFT RAM Address signal FFT_SEL_sig : std_logic ; -- FFT RAM Access signal FFT_SEL_EXT_sig : std_logic ; signal CS_0_X_sig : std_logic ; -- Real RAM Chip Select signal CS_1_X_sig : std_logic ; -- Real RAM Chip Select signal CAP_SEL_sig : std_logic ; signal PHASE_K_sig : std_logic; signal PHASE_I_sig : std_logic; signal TRI_RD_DATA_sig : std_logic_vector(19 downto 0) ; signal TRI_ADDR_sig : std_logic_vector (9 downto 0); signal UP_ADDR : std_logic_vector(9 downto 0); signal UP_RD_DATA : std_logic_vector(15 downto 0); signal UP_WR_DATA : std_logic_vector(15 downto 0); signal UP_OE_N : std_logic; signal UP_WE_N : std_logic; signal UP_IMAG_SEL : std_logic; signal CAP_START : std_logic; signal FFT_START : std_logic;