Net fpga_0_DIP_Switches_GPIO_IO_I_pin<0> LOC=P30 | IOSTANDARD = LVCMOS33;
Net fpga_0_DIP_Switches_GPIO_IO_I_pin<1> LOC=P13 | IOSTANDARD = LVCMOS33;

Net fpga_0_LEDS_GPIO_IO_O_pin<0> LOC=P68 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDS_GPIO_IO_O_pin<1> LOC=P67 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDS_GPIO_IO_O_pin<2> LOC=P66 | IOSTANDARD = LVCMOS33;
Net fpga_0_LEDS_GPIO_IO_O_pin<3> LOC=P65 | IOSTANDARD = LVCMOS33;

Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=P88;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=P89;