component IirSerial3 Port ( RST_N : In std_logic; MCLK : In std_logic; FSCLK : In std_logic; A0 : In std_logic_vector(17 downto 0); A1 : In std_logic_vector(17 downto 0); A2 : In std_logic_vector(17 downto 0); B1 : In std_logic_vector(17 downto 0); B2 : In std_logic_vector(17 downto 0); C0 : In std_logic_vector(17 downto 0); C1 : In std_logic_vector(17 downto 0); C2 : In std_logic_vector(17 downto 0); D1 : In std_logic_vector(17 downto 0); D2 : In std_logic_vector(17 downto 0); E0 : In std_logic_vector(17 downto 0); E1 : In std_logic_vector(17 downto 0); E2 : In std_logic_vector(17 downto 0); F1 : In std_logic_vector(17 downto 0); F2 : In std_logic_vector(17 downto 0); XIN : In std_logic_vector(15 downto 0); YOUT : Out std_logic_vector(15 downto 0) ); end component; component S_P Port ( RST_N : In std_logic; MCLK : In std_logic; SDATA : In std_logic; LRCLK : In std_logic; BCLK : In std_logic; LDATA : Out std_logic_vector(15 downto 0); RDATA : Out std_logic_vector(15 downto 0) ); end component; component P_S Port ( RST_N : In std_logic; MCLK : In std_logic; LATCH_L : In std_logic; LATCH_R : In std_logic; BCLK : In std_logic; LDATA : In std_logic_vector(15 downto 0); RDATA : In std_logic_vector(15 downto 0); SDATA : Out std_logic ); end component; component TimingGen Port ( RST_N : In std_logic; MCLK : In std_logic; ALRCLK : Out std_logic; ABCLK : Out std_logic; AMCLK : Out std_logic ); end component; component initial_latch Port ( RST_N : In std_logic; MCLK : In std_logic; ADATA : In std_logic; ADATAO : Out std_logic; ABCLK : In std_logic; ABCLKO : Out std_logic; ALRCLK : In std_logic; ALRCLKO : Out std_logic; ALRCLKO2 : Out std_logic ); end component; signal ldata_sig : std_logic_vector( 15 downto 0 ); signal rdata_sig : std_logic_vector( 15 downto 0 ); signal LOUT_sig : std_logic_vector(15 downto 0); signal ROUT_sig : std_logic_vector(15 downto 0); signal rst_n_dly0 : std_logic; signal rst_n_dly1 : std_logic; signal AMCLK_sig : std_logic; signal ALRCLK_sig : std_logic; signal ABCLK_sig : std_logic; signal ADATA_latch : std_logic; signal ALRCLK_latch_l : std_logic; signal ALRCLK_latch_r : std_logic; signal ABCLK_latch : std_logic; signal A0 :std_logic_vector(17 downto 0); signal A1 :std_logic_vector(17 downto 0); signal A2 :std_logic_vector(17 downto 0); signal B1 :std_logic_vector(17 downto 0); signal B2 :std_logic_vector(17 downto 0); signal C0 :std_logic_vector(17 downto 0); signal C1 :std_logic_vector(17 downto 0); signal C2 :std_logic_vector(17 downto 0); signal D1 :std_logic_vector(17 downto 0); signal D2 :std_logic_vector(17 downto 0); signal E0 :std_logic_vector(17 downto 0); signal E1 :std_logic_vector(17 downto 0); signal E2 :std_logic_vector(17 downto 0); signal F1 :std_logic_vector(17 downto 0); signal F2 :std_logic_vector(17 downto 0);