-------------------------------------------------------------------
gen_rst_n_dly : process( MCLK ) 
begin
  if( MCLK'event and MCLK = '1' ) then
    rst_n_dly1 <= rst_n_dly0;
    rst_n_dly0 <= RST_N;
  end if;
end process;

-------------------------------------------------------------------
IirSerial3_1 : IirSerial3 port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          FSCLK => ALRCLK_latch_l,
          A0 => a0,
          A1 => a1,
          A2 => a2,
          B1 => b1,
          B2 => b2,
          C0 => c0,
          C1 => c1,
          C2 => c2,
          D1 => d1,
          D2 => d2,
          E0 => e0,
          E1 => e1,
          E2 => e2,
          F1 => f1,
          F2 => f2,
          XIN => ldata_sig,
          YOUT => LOUT_sig );

-------------------------------------------------------------------
IirSerial3_2 : IirSerial3 port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          FSCLK => ALRCLK_latch_r,
          A0 => a0,
          A1 => a1,
          A2 => a2,
          B1 => b1,
          B2 => b2,
          C0 => c0,
          C1 => c1,
          C2 => c2,
          D1 => d1,
          D2 => d2,
          E0 => e0,
          E1 => e1,
          E2 => e2,
          F1 => f1,
          F2 => f2,
          XIN => rdata_sig,
          YOUT => ROUT_sig );

-------------------------------------------------------------------
S_P_1 : S_P port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          SDATA => ADATA_latch,
          LRCLK => ALRCLK_latch_l,
          BCLK => ABCLK_latch,
          LDATA => ldata_sig,
          RDATA => rdata_sig ); 

-------------------------------------------------------------------
P_S_1 : P_S port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          LATCH_L => ALRCLK_latch_l,
          LATCH_R => ALRCLK_latch_r,
          BCLK => ABCLK_latch,
          LDATA => LOUT_sig, 
          RDATA => ROUT_sig, 
          SDATA => DDATA );

-------------------------------------------------------------------
TimingGen_1 : TimingGen port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          ALRCLK => ALRCLK_sig,
          ABCLK => ABCLK_sig,
          AMCLK => AMCLK_sig ); 

-------------------------------------------------------------------
initial_latch_1 : initial_latch port map (
          RST_N => rst_n_dly1,
          MCLK => MCLK,
          ADATA => ADATA,
          ADATAO => ADATA_latch, 
          ABCLK => ABCLK_sig,
          ABCLKO => ABCLK_latch, 
          ALRCLK => ALRCLK_sig,
          ALRCLKO => ALRCLK_latch_l, 
          ALRCLKO2 => ALRCLK_latch_r ); 

-------------------------------------------------------------------
  ALRCLK <= ALRCLK_sig;
  ABCLK <= ABCLK_sig;
  AMCLK <= AMCLK_sig;
  
  DLRCLK <= ALRCLK_sig;
  DBCLK <= ABCLK_sig;
  DMCLK <= AMCLK_sig;

          PWDN_N <= '1';
          BYPAS <= '1';
          MODE <= "00";
          FMT <= "00";
          OSR <= '0';
          ML <= '0';
          MC <= '0';
          MD <= '0';

-------------------------------------------------------------------
process( slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4 )
begin 
  for i in 17 downto 0 loop
    A0(i) <= slv_reg0(31-i);
    A1(i) <= slv_reg1(31-i);
    A2(i) <= slv_reg2(31-i);
    B1(i) <= slv_reg3(31-i);
    B2(i) <= slv_reg4(31-i);
  end loop;
end process;
 
-------------------------------------------------------------------
process( slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9 )
begin 
  for i in 17 downto 0 loop
    C0(i) <= slv_reg5(31-i);
    C1(i) <= slv_reg6(31-i);
    C2(i) <= slv_reg7(31-i);
    D1(i) <= slv_reg8(31-i);
    D2(i) <= slv_reg9(31-i);
  end loop;
end process;
 
-------------------------------------------------------------------
process( slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14 )
begin 
  for i in 17 downto 0 loop
    E0(i) <= slv_reg10(31-i);
    E1(i) <= slv_reg11(31-i);
    E2(i) <= slv_reg12(31-i);
    F1(i) <= slv_reg13(31-i);
    F2(i) <= slv_reg14(31-i);
  end loop;
end process;