component nios2e is
	port (
		clk_clk                        : in    std_logic := 'X'; -- clk
		reset_reset_n                  : in    std_logic := 'X'; -- reset_n
		sda_external_connection_export : inout std_logic := 'X'; -- export
		scl_external_connection_export : inout std_logic := 'X';  -- export
		colsel_external_connection_export : in   std_logic_vector(3 downto 0);                     -- export
		ansaddr_external_connection_export : out   std_logic_vector(8 downto 0);                     -- export
		ansdata_external_connection_export : in    std_logic_vector(5 downto 0)  := (others => 'X')  -- export
	);
	end component nios2e;