component nios2e is
		port (
            clk_clk                           : in    std_logic                     := 'X'; -- clk
            reset_reset_n                     : in    std_logic                     := 'X'; -- reset_n
            scl_external_connection_export    : inout std_logic                     := 'X'; -- export
            sda_external_connection_export    : inout std_logic                     := 'X'; -- export
            thresh_external_connection_export : out   std_logic_vector(13 downto 0) ;        -- export
            uart_0_external_connection_rxd    : in    std_logic                     := 'X'; -- rxd
            uart_0_external_connection_txd    : out   std_logic;                             -- txd
            ansinfo_external_connection_export : in    std_logic_vector(31 downto 0) := (others => 'X');  -- export
            ansaddr_external_connection_export : out   std_logic_vector(8 downto 0);                     -- export
            ansdata_external_connection_export : in    std_logic_vector(5 downto 0)  := (others => 'X')  -- export
		);
	end component nios2e;