|Execute VHDL simulation|
|This time, I used ModelSim PE VHDL 6.3c (Mentor Graphics, Inc.). The project
name is tb_fft.
Extract this archive and add all files to the project.
The following is an example of compile-order, that is basically from lower module.
After successful compilation, let's start simulation and break it about 16ms. The first 10ms is the period to initialize RAMs in fftrtl_1024.vhd. Note that this is "test mode" and FixedIn.txt and FixedIn4AD.txt should reside in the same directory.
FFT starts around 15ms and finishes soon. The execution period is 206us (= 10,300/50MHz). That means 1024-point FFT is computed only in 10k cycles.
This dsPIC, that is programmed in C language, computes 512-point FFT in 50k cycles. Therefore VHDL is about ten times faster than C.