VHDL description and simulation
RTL simulation is necessary to make up a correct design in VHDL. Let's compare simulation result with previous C's result.

(1) RTL stands for Register Transfer Level, that is a way to describe synchronous circuits. F/Fs (flip-flop) work with clocks and combination logic resides between F/Fs. RTL is
more abstract than Gate Level and less abstract than Behavior Level.

1024-point FFT has (1024/2)log2(1024) = 5120 complex multiplications. This FFT consume two cycles for a multiplication, so that 5120 x 2 = 10,240, and needs some overhead, totally it's consumes 10,300 cycles.
(1) FFT and testbench in VHDL
  • FFT in VHDL. (RTL, see CoffeeBreak 1)
  • Inject signals from environment to FFT.
(2) Execute VHDL simulation
  • Compile and run the FFT and testbench.
  • Only 10,300 cycles to compute 1024-point FFT. (see CoffeeBreak 2)
(3) Save the result of simulation
  • Save the data inside RAM to a text file.
  • Use List window of ModelSim.
(4) Compare the simulation with C
  • Re-run FftFixed (VC++ project).
  • Copy the simulation results and compare it.


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